Integrated circuits (ICs) typically include numerous elements that are fabricated on silicon wafers. During the fabrication process, a “sandwich” of various conducting and non-conducting layers is laid down on a silicon wafer substrate. The conducting layers typically include layers of diffusion (wherein a chemical substance is diffused into the silicon substrate) and polysilicon, as well as several metal layers. The conducting layers are isolated from each other using intermediate layers of non-conducting material (e.g., silicon-dioxide), and electrically connected to one another by way of openings in these isolating layers. By convention, these openings are called “contacts” when the connection is between a diffusion layer or a polysilicon layer and the bottommost metal layer, and “vias” when the connection is between two different metal layers.
During the fabrication process, various types of manufacturing defects can occur. For example, a “short” (a short circuit) can appear between two layers of the same type. A short is an inadvertent electrical connection between two constructs. A metal short can occur, for example, when excess metal is laid down during processing such that each metal structure is slightly larger than it is intended to be. Because there are great advantages to using the smallest possible structures in designing an IC, wafer fabrication plants typically push the envelope by defining minimum separations that are the smallest feasible. Therefore, shorts are a common type of defect in integrated circuits.
Another type of defect commonly found in ICs is an “open”@ (an open circuit). An open is an inadvertent disconnect between two points designed to be electrically connected. A metal open can occur, for example, when insufficient metal is deposited in a particular location along a narrow metal line. In this case, a portion of the narrow metal line can effectively disappear from an IC and little or no current is conducted along that portion of the metal line.
An open can also occur in a via or contact (i.e., an opening in the non-conducting layer), when, for example, the contact or via etch is insufficiently deep to reach the underlying conducting layer. Also common are “partial opens” or resistive contacts and vias, where only a very small area contacts the underlying conducting layer or some degradation of the conducting material in the contact or via has occurred. Resistive contacts and vias not only affect the circuit speed and functionality, but are also considered unreliable, because they tend to become more open (more resistive) after the application of high currents.
Methods have been devised to test the processing of a silicon wafer by including a “test chip” at various points on the wafer. The test chip (also called a “Defect Monitor Vehicle”, or DMV) includes structures intended for the purpose of testing for shorts and opens. If shorts and opens are found when testing the DMV, it is logical to assume that similar defects will be found in the other ICs on the wafer. Because the DMV is quick and easy to test, valuable test time is saved by discarding wafers that include high numbers of shorts and opens in the DMVs. Additionally, the DMVs can be used to track down problem areas in the fabrication process.
Voogel describes one such Defect Monitor Vehicle in U.S. Pat. No. 6,281,696 B1, which is incorporated herein by reference. Voogel's DMV contains a core array that includes interleaved “fork” structures for detecting shorts and serpentine structures for detecting opens in diffusion, polysilicon, and metal layers. Voogel also shows and describes switches, decoders, and control circuitry for selectively testing each of these elements within the core array.
Voogel's test structure is useful in detecting and locating shorts and opens generated during the IC fabrication process. However, Voogel's test structure does not detect resistive contacts and vias, because the effect of a single resistive point in an array is often too small to be noticed. Also, it is not possible to send large currents through the resistive chains in Voogel's array, because the total resistance of the chain is too high. To apply a large current to such a chain would require a voltage far exceeding what the control transistors can handle.
Therefore, to test for resistive contacts and vias requires an improvement to the accuracy of measuring the resistance of a resistive chain (e.g., the metal line or contact or via chain). Preferably, the resistance measurement should be accurate to within a few percentage points. Any structure that has more than a few percentage points of change in resistance value (i.e., enough change to be measured accurately) probably contains at least one resistive contact or via that has changed in value.
It is also desirable to allow for higher current stresses of the resistive structures in order to monitor the effect of the higher currents on the structures.
Any high speed switching circuitry within an IC has metal lines, contacts, and vias that conduct large amounts of current for a short time. For example, when the input signal driving an inverter changes state, both the N and P channel transistors in the inverter are momentarily on at the same time, causing a “crossbar current”. Also, there is a high current flow through one of the N and P channel transistors as the capacitive load of the inverter is charged. These high current stresses can change the resistance of the conducting layers in an IC, which can adversely affect the timing and even the functionality of the IC. The high current stresses can also reshape the structures forming the IC circuits, causing additional shorts and opens that were not present after wafer fabrication.
Therefore, it is desirable to provide structures and methods for detecting and locating changes in resistance and/or shorts in ICs that have been subjected to high current stress.